1 of 10 n n n n high speed/low power - speeds ranging from 5ns to 25ns - power as low as 67ma at 25mhz n n n n electrically erasable technology - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs n n n n development/programmer support - third party software and programmers - ict place development software and pds-3 programmer n n n n architectural flexibility - 132 product term x 44 input and array - up to 22 inputs and 10 outputs - up to 12 configurations per macrocell - synchronous preset, asynchronous clear - independent output enables - 24-pin dip/soic/tssop and 28-pin plcc n n n n application versatility - replaces random logic - pin and jedec compatible with 22v10 - enhanced architecture fits more logic than ordinary plds features the peel?22cv10a is a programmable electrically eras- able logic (peel?) device providing an attractive alterna- tive to ordinary plds. the peel?22cv10a offers the performance, flexibility, ease of design and production prac- ticality needed by logic designers today. the peel?22cv10a is available in 24-pin dip, soic, tssop and 28-pin plcc packages (see figure 1), with speeds ranging from 5ns to 25ns and with power consumption as low as 67ma. ee-reprogrammability provides the conve- nience of instant reprogramming for development and a reusable production inventory, minimizing the impact of pro- gramming changes or errors. ee-reprogrammability also improves factory testability, thus ensuring the highest qual- ity possible. the peel?22cv10a is jedec file compati- ble with standard 22v10 plds. eight additional configurations per macrocell (a total of 12) are also avail- able by using the + software/programming option (i.e., 22cv10a+). the additional macrocell configurations allow more logic to be put into every design. programming and development support for the peel?22cv10a are pro- vided by popular third-party programmers and development software. ict also offers free place development software and a low-cost development system (pds-3). general description dip *optional extra ground pin for -5/-7/i-7 speed grade. plcc 1 2 3 4 5 6 7 8 i/clk i i i i i i i vcc i/o i/o i/o i/o i/o i/o i/o 24 23 22 21 20 19 18 17 9 10 i i i/o i/o 16 15 11 12 i gnd i/o i 14 13 tssop soic figure 1. pin configuration figure 2. block diagram commercial/ industrial cmos programmable electrically erasable logic device peel? 22cv10a -5/-7/-10/-15/-25
2 of 10 peel tm 22cv10a 131 124 130 111 98 83 82 66 49 33 20 21 2 0 9 10 34 48 65 121 110 97 i i i i i i i i/clk i i i macro cell asynchronous clear (to all macrocells) macro cell macro cell macro cell macro cell macro cell macro cell macro cell macro cell macro cell synchronous preset (to all macrocells) i/o i/o i/o i/o i/o i/o i/o i/o i/o i i/o figure 3. peel?22cv10a logic array diagram
3 of 10 peel tm 22cv10a function description the peel?22cv10a implements logic functions as sum- of-products expressions in a programmable-and/ fixed-or logic array. user-defined functions are created by program- ming the connections of input signals into the array. user- configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the peel?22cv10a architecture is illustrated in the block diagram of figure 2. twelve dedicated inputs and 10 i/os provide up to 22 inputs and 10 outputs for creation of logic functions. at the core of the device is a programmable elec- trically-erasable and array which drives a fixed or array. with this structure, the peel?22cv10a can implement up to 10 sum-of-products logic expressions. associated with each of the 10 or functions is an i/o mac- rocell which can be independently programmed to one of 4 different configurations. the programmable macrocells allow each i/o to create sequential or combinatorial logic functions with either active-high or active-low polarity. and/or logic array the programmable and array of the peel?22cv10a (shown in figure 3) is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 44 input lines: 24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 i/os 132 product terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14 and 16) used to form logical sums 10 output enable terms (one for each i/o) 1 global synchronous present term 1 global asynchronous clear term at each input-line/product-term intersection there is an eeprom memory cell which determines whether or not there is a logical connection at that intersection. each prod- uct term is essentially a 44-input and gate. a product term which is connected to both the true and complement of an input signal will always be false, and thus will not affect the or function that it drives. when all the connections on a product term are opened, a dont care state exists and that term will always be true. when programming the peel?22cv10a, the device programmer first performs a bulk erase to remove the previous pattern. the erase cycle opens every logical connection in the array. the device is then configured to perform the user-defined function by programming selected connections in the and array. (note that peel? device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.) variable product term distribution the peel?22cv10a provides 120 product terms to drive the 10 or functions. these product terms are distributed among the outputs in groups of 8, 10, 12, 14 and 16 to form logical sums (see figure 3). this distribution allows opti- mum use of device re-sources. programmable i/o macrocell the output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configura- tion of the peel?22cv10a to the precise r equirements of their designs. macrocell architecture each i/o macrocell, as shown in figure 4, consists of a d- type flip-flop and two signal-select multiplexers. the config- uration of each macrocell is determined by the two eeprom bits contro lling these multiplexers (refer to table 1). these bits determine output polarity and output type (registered or non-registered). equivalent circuits for the four macro-cell configurations are illustrated in figure 5. output type the signal from the or array can be fed directly to the out- put pin (combinatorial function) or latched in the d-type flip- flop (registered function). the d-type flip-flop latches data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. when the synchronous preset term is satisfied, the q output of the register will be set high at the next rising edge of the clock input. satisfying the asynchronous clear term will set q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or dis- abled under the control of its associated programmable out- put enable product term. when the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is driven into the high-impedance state. under the control of the output enable term, the i/o pin can function as a dedicated input, a dedicated output, or a bi- directional i/o. opening every connection on the output
4 of 10 peel tm 22cv10a enable term will permanently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will always be logically false and the i/o will function as a dedicated input. input/feedback select when configuring an i/o macrocell to implement a regis- tered function (configurations 1 and 2 in figure 5), the q output of the flip-flop drives the feedback term. when con- figuring an i/o macrocell to implement a combinatorial function (configurations 3 and 4 in figure 5), the feedback signal is taken from the i/o pin. in this case, the pin can be used as a dedicated input or a bi-directional i/o. (refer also to table 1.) additional macro cell configurations besides the standard four-configuration macrocell shown in figure 5, each peel?22cv10a provides an additi onal eight configurations that can be used to increase design flexibility. the configurations are the same as provided by the peel?18cv8 and peel?22cv10az. however, to maintain jedec file compatibility with standard 22v10 plds the additional configurations can only be utilized by specifying the peel?22cv10a+ or peel? 22cv10a++ for logic assembly and programing. to reference these additional configurations please refer to the peel?22cv10a+ specifications at the end of this data sheet. design security the peel?22cv10a provides a special eeprom secu- rity bit that prevents unauthorized reading or copying of designs programmed into the device. the security bit is set by the pld programmer, either at the conclusion of the pro- gramming cycle or as a separate step after the device has been programmed. once the security bit is set, it is impos- sible to verify (read) or program the peel? until the entire device has first been erased with the bulk-erase function. signature word the signature word feature allows a 24-bit code to be pro- grammed into the peel?22cv10a if the peel?22cv10a+ or peel? 22cv10a++ software option is used. the code can be read back even after the security bit has been set. the signature word can be used to iden- tify the pattern programmed into the device or to record the design revision, etc. figure 4. block diagram of the peel? 22cv10a i/o macrocell.
5 of 10 peel tm 22cv10a figure 5. equivalent circuits for the four configurations of the peel?22cv10a i/o macro- cell table 1. peel? 22cv10a macrocell configuration bits configuration input/feedback select output select # a b 1 0 0 register feedback register active low 21 0 active high 30 1 bi-directional i/o combinatorial active low 41 1 active high
6 of 10 peel tm 22cv10a additional macrocell configurations besides the standard four-configuration macrocells, each peel?22cv10a provides an additional eight configura- tions (twelve total) that can be used to increase design flex- ibility (see figure 6 and table 2). for logic assembly of all twelve configurations, specify peel?22cv10a+. also, select the peel?22cv10a+ for programming. configuration input/feedback select output select # a b c d 1 1 1 1 1 bi-directional i/o register active low 2 0 1 1 1 active high 3 1 0 1 1 combinatorial active low 4 0 0 1 1 active high 5 1 1 1 0 combinatorial feedback register active low 6 0 1 1 0 active high 7 1 0 1 0 combinatorial active low 8 0 0 1 0 active high 9 1 1 0 0 register feedback register active low 10 1 0 0 0 active high 11 1 0 0 0 combinatorial active low 12 0 0 0 0 active high figure 6. equivalent circuits for the twelve configurations of the peel?22cv10a+ i/o macro- table 2. peel? 22cv10a+ macrocell configuration bits
7 of 10 peel tm 22cv10a table 6. absolute maximum ratings symbol parameter conditions ratings unit v cc supply voltage relative to ground -0.5 to + 7.0 v v i , v o voltage applied to any pin 2 relative to ground 1 -0.5 to v cc + 0.6 v i o output current per pin (i ol , i oh )25ma t st storage temperature -65 to + 150 c t lt lead temperature soldering 10 seconds +300 c table 7. operating ranges symbol parameter conditions min max unit v cc supply voltage commercial 4.75 5.25 v industrial 4.5 5.5 t a ambient temperature commercial 0 +70 c industrial -40 +85 t r clock rise time see note 3 20 ns t f clock fall time see note 3 20 ns t rvcc v cc rise time see note 3 250 ms table 8. d.c. electrical characteristics over the recommended operating conditions symbol parameter conditions min max unit v oh output high voltage v cc = min, i oh = -4.0ma 2.4 v v ohc output high voltage - cmos 13 v cc = min, i oh = -10a v cc - 0.3 v v ol output low voltage - ttl v cc = min, i ol = 16ma 0.5 v v olc output low voltage - cmos 13 v cc = min, i oh = -10a 0.15 v v ih input high level 2.0 v cc + 0.3 v v il input low level -0.3 0.8 v i il input leakage current v cc = max, v in = gnd v in v cc 10 a i oz output leakage current i/o = high-z, gnd v o v cc 10 a i sc output short circuit current v cc = 5v, vo = 0.5v 9 , t a = 25c -30 -135 ma icc 10 v cc current (see cr-1 for typical i cc ) v in = 0v or 3v f = 25mhz all outputs disabled 4 -5 140 ma -7/i-7 140/155 -10/i-10 135/145 -15/i-15 135/145 -25/i-25 67/75 c in 7 input capacitance t a = 25c, v cc = 5.0v @ f = 1 mhz 6pf c out 7 output capacitance 12 pf this device has been designed and tested for the recommended operating conditions. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause per- manent damage.
8 of 10 peel tm 22cv10a table 9. a.c. electrical characteristics symbol parameter -5 -7 / i-7 -10 / i-10 -15 / i-15 -25 / i-25 unit min max min max min max min max min max t pd input 5 to non-registered output 5 7.5 10 15 25 ns t oe input 5 to output enable 6 5 7.5 10 15 25 ns t od input5 to output disable 6 5 7.5 10 15 25 ns t co1 clock to output 4 5.5 6 8 15 ns t co2 clock to comb. output delay via internal registered feedback 7.510121735ns t cf clock to feedback 2.5 3.5 4 5 9 ns t sc input 5 or feedback setup to clock 335815ns t hc input 5 hold after clock 00000ns t cl , t ch clock low time, click high time 8 2.5 3 4 6 13 ns t cp min clock period ext (t sc + t co1 )7 8.5 11 18 30 ns f max1 internal feedback (1 tsc + t cf ) 12 181.6 142 111 76.9 41.6 mhz f max2 external feedback (1/t cp ) 12 142.8 117 90.9 62.5 33.3 mhz f max3 no feedback (1/t cl + t ch ) 12 200 166 125 83.3 38.4 mhz t aw asynchronous reset pulse width 5 7.5 10 15 25 ns t ap input 5 to asynchronous reset 5 7.5 10 15 25 ns t ar asynch. reset recovery time 5 7.5 10 15 25 ns t reset power-on reset time for registers in clear state 55555s inputs, i/o, registered feedback, synchronous preset clock asynchronous reset registered outputs combinatorial outputs notes 1. minimum dc input is -0.5v, however inputs may undershoot to -2.0v for periods less than 20ns. 2. v i and v o are not specified for program/verify operation. 3. test points for clock and v cc in t r , t f are referenced at 10% and 90% levels. 4. i/o pins are 0v and 3v. 5. input refers to an input pin signal. 6. t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh -0.1v or v ol +0.1v; v ref =v l see test loads in section 5 of this data book. 7. capacitances are tested on a sample basis. 8. test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 9. test one output at a time for a duration of less than 1sec. 10. icc for a typical application: this parameter is tested with the device programmed as an 8-bit counter. 11. peel? device test loads are specified in section 6 of this data book. 12. parameters are not 100% tested. specifications are based on initial characterization and are tested after any design or process modifica- tion which may affect operational frequency. 13. available only for 22cv10a -15/i-15/-25/i-25 grades. switching waveforms over the operating range 8,11
9 of 10 peel tm 22cv10a table 6. ordering information part number speed temperature package peel 22cv10aj-5 5ns c j28 peel22cv10ap-7 7.5ns c p24 peel22cv10api-7 i peel 22cv10aj-7 7.5ns c j28 peel 22cv10aji-7 i peel 22cv10as-7 7.5ns c s24 peel 22cv10asi-7 i peel 22cv10at-7 7.5ns c t24 peel 22cv10ati-7 i peel 22cv10ap-10 10ns c p24 peel 22cv10api-10 i peel 22cv10aj-10 10ns c j28 peel 22cv10aji-10 i peel 22cv10as-10 10ns c s24 peel 22cv10asi-10 i peel 22cv10at-10 10ns c t24 peel 22cv10ati-10 i peel 22cv10ap-15 15ns c p24 peel 22cv10api-15 i peel 22cv10aj-15 15ns c j28 peel 22cv10aji-15 i peel 22cv10as-15 15ns c s24 peel 22cv10asi-15 i peel 22cv10at-15 15ns c t24 peel 22cv10ati-15 i peel 22cv10ap-25 25ns c p24 peel 22cv10api-25 i peel 22cv10at-25 25ns c t24 peel 22cv10ati-25 i peel 22cv10aj-25 25ns c j28 peel 22cv10aji-25 i peel 22cv10as-25 25ns c s24 peel 22cv10asi-25 i
10 of 10 peel tm 22cv10a part number device peel? 22cv10a pi-25 package p = plastic 300mil dip j = plastic (j) leaded chip carrier (plcc) s = soic t = tssop temperature range and power options (blank) = commercial 0 to 70c i = industrial -40 to +85c speed -5 = 5ns tpd -7 = 7.5ns tpd -10 = 10ns tpd -15 = 15ns tpd -25 = 25ns tpd suffix
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